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Self-adjusting sensing circuit without speed penalty for reliable STT-MRAM

Self-adjusting sensing circuit without speed penalty for reliable STT-MRAM

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A self-adjusting sensing circuit spin-torque transfer magnetic random access memory (STT-MRAM) is proposed. STT-MRAM is considered to be the most promising candidate among the new emerging memories. However, read performance has emerged as a new bottleneck, because of its low tunnelling magneto-resistance ratio (TMR) and low read current. The proposed self-adjusting sensing circuit shows an improved sensing margin, overcoming the weaknesses of the STT-MRAM. The proposed circuit using Verilog-A model, a 65 nm complementary metal–oxide–semiconductor process also evaluated, and Monte Carlo analysis. The results of analysis show that the proposed circuit ensures a certain sensing margin, which is more than 200 mV in TMR 150% and about 50 mV in TMR 100%.

References

    1. 1)
      • 1. Li, H., Chen, Y.: ‘Non-volatile memory design: magnetic, resistive, and phase change’ (CRC Press, Boca Raton, FL, USA, 2011, 1st edn.).
    2. 2)
      • 2. Noguchi, H., Ikegami, K., Takaya, S., et al: ‘4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write/read-modify-write scheme’. Int. Conf. Solid-State Circuits, San Fransisco, CA, USA, February 2016, pp. 132133, doi: 10.1109/ISSCC.2016.7417942.
    3. 3)
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