In this Letter, a novel 1200 V FS- insulated gate bipolar transistors (IGBT) is proposed to improve the trade-off between avalanche ruggedness and on-state voltage drop. The proposed IGBT features the high doping and thin n-layer under trench gates and we call it the electric field modulation layer (EFM layer). Under the avalanche condition, the EFM layer can form the sharp electric filed distribution in the EFM layer and the avalanche multiplication is constrained in the thin EFM layer. The difference between the holes and electrons due to the avalanche multiplication effect at the emitter side of the IGBT is minished. Therefore, the negative difference resistance in the avalanche I–V curve caused by the difference between the holes and electrons is eliminated. As a consequence, the avalanche ruggedness of the EFM-IGBT is improved. In the on-state, the high doping EFM layer can store the carriers and the on-state voltage drop of the EFM-IGBT is reduced to 1.48 V at 200 A/cm². Finally, the EFM-IGBT improves the trade-off between avalanche ruggedness and on-state voltage drop.

References

1. 1)
  - 2. Pendharkar, S., Trivedi, M., Shenai, K.: ‘Electrothermal simulations in punchthrough and nonpunchthrough IGBT's’, IEEE Trans. Electron Dev., 1998, 45, (10), pp. 2222–2231 (doi: 10.1109/16.725257).
2. 2)
  - 7. Breglio, G., Irace, A., Napoli, E., et al: ‘Detection of localized UIS failure on IGBTs with the aid of lock-in thermography’, Microelectron. Rel., 2008, 48, (8–9), pp. 1432–1434 (doi: 10.1016/j.microrel.2008.06.042).
3. 3)
  - 6. Irace, A., Spirito, P., Riccio, M., Breglio, G.: ‘Voltage drops, sawtooth oscillations and HF bursts in breakdown current and voltage waveforms during UIS experiments’. Proc. 24th ISPSD, Bruges, Belgium, June 2012, pp. 165–168.
4. 4)
  - 1. Hefner, C.-C., Allen, R., Berning, D.W., Bernstein, J.B.: ‘Failure dynamics of the IGBT during turn-off for unclamped inductive loading conditions’, IEEE Trans. Ind. Appl., 2000, 36, (2), pp. 614–624 (doi: 10.1109/28.833780).
5. 5)
  - 9. Spirito, P., Breglio, G., Irace, A., et al: ‘Physics of the negative resistance in the avalanche I–V curve of field stop IGBTs: collector design rules for improved ruggedness’, IEEE Trans. Electron. Dev., 2014, 61, (5), pp. 1457–1463 (doi: 10.1109/TED.2014.2311169).
6. 6)
  - 8. Breglio, G., Irace, A., Napoli, E., Riccio, M., Spirito, P.: ‘Experimental detection and numerical validation of different failure mechanisms in IGBTs during unclamped inductive switching’, IEEE Trans. Electron. Dev., 2013, 60, (2), pp. 563–570 (doi: 10.1109/TED.2012.2226177).
7. 7)
  - 11. Takahashi, T., Tomomatsu, Y., Sato, K.: ‘CSTBT (III) as the next generation IGBT’. Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th Int. Symp. on, Orlando, FL, USA, May 2008, pp. 72–75.
8. 8)
  - 3. Riccio, M., De Falco, G., Maresca, L., et al: ‘3D electro-thermal simulations of wide area power devices operating in avalanche condition’, Microelectron. Rel., 2012, 52, (9–10), pp. 2385–2390 (doi: 10.1016/j.microrel.2012.06.133).
9. 9)
  - 5. Riccio, M., Irace, A., Breglio, G., Spirito, P., Napoli, E., Mizuno, Y.: ‘Electro-thermal instability in multi-cellular trench-IGBTs in avalanche condition: experiments and simulations’. Proc. IEEE 23rd ISPSD, San Diego, CA, USA, May 2011, pp. 124–127.
10. 10)
  - 10. Riccio, M., Maresca, L., De Falco, G., et al: ‘Cell pitch influence on the current distribution during avalanche operation of trench IGBTs: design issues to increase UIS ruggedness’. 2014 IEEE 26th Int. Symp. on Power Semiconductor Devices & IC's (ISPSD), Waikoloa, HI, USA, June 2014, pp. 111–114.
11. 11)
  - 4. Muller, A., Pfirsch, F., Silber, D.: ‘Trench IGBT behaviour near to latch-up conditions’. Proc. 17th Int. Symp. ISPSD, Santa Barbara, CA, USA, May 2005, pp. 255–258.

1200 V FS-IGBT with electric field modulation layer to improve trade-off between avalanche ruggedness and on-state voltage drop

References

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