http://iet.metastore.ingenta.com
1887

Dual CDS scheme embedded in SAR-based ADCs for low-noise CMOS imagers without a PGA

Dual CDS scheme embedded in SAR-based ADCs for low-noise CMOS imagers without a PGA

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A dual correlated double sampling (CDS) scheme, which can be embedded into a successive approximation register (SAR) or SAR/single-slope analogue-to-digital converters (ADCs) for low-noise CMOS imagers without the use of a power-consuming programmable gain amplifier (PGA) is proposed. To reduce the noise of the readout channel, the proposed dual CDS scheme removes the sampling error, which occurs in the capacitor digital-to-analogue converter (DAC), by storing only a reset voltage of the pixel into the capacitor DAC. In addition, without using the PGA, it amplifies the output of the readout channel by controlling the reference voltages of the ADC. The readout channel using the proposed CDS scheme was designed using a 90 nm CMOS imager process technology. The simulation results show that the signal-to-noise-distortion ratio of the readout channel using the proposed dual CDS scheme is 81.8 dB, which is an improvement of 10.8 dB over the digital CDS scheme. In addition, the output of the readout channel is amplified without the use of a PGA.

References

    1. 1)
    2. 2)
    3. 3)
      • 3. Honda, H., Osawa, S., Shoda, M., et al: ‘A 1-inch optical format, 14.2M-pixel, 80 fps CMOS image sensor with a pipelined pixel reset and readout operation’. IEEE Symp. on VLSI Circuits, Kyoto, Japan, June 2013, pp. 1214.
    4. 4)
    5. 5)
    6. 6)
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.3706
Loading

Related content

content/journals/10.1049/el.2016.3706
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Correspondence
This article has following corresponding article(s):
in brief
This is a required field
Please enter a valid email address