access icon free Low-cost multi-standard video transform core using time-distribution scheme

Cost-effective two-dimensional (2D) discrete cosine transform (DCT) and inverse DCT architectures capable of supporting multiple standards of MPEG, H.264 and VC-1 are presented. The proposed core utilises a 1D core and a transposed memory to achieve a low cost design. Multi-level factor share is implemented in conjunction with distributed arithmetic in a system to enable the sharing of the coefficient matrix circuit in order to reduce hardware costs. The proposed approach employs a time-distribution scheme to enable the simultaneous processing of the first and second dimensions to enhance throughput. A high efficiency of this approach was verified by fabricating a test chip using the TSMC 0.18 μm CMOS process. The architecture has an operating frequency of 200 MHz, and throughput of 800 M-pixels/s with a gate count of 44.5 K.

Inspec keywords: inverse transforms; distributed arithmetic; video coding; CMOS integrated circuits; discrete cosine transforms

Other keywords: transposed memory; frequency 200 MHz; cost-effective two-dimensional discrete cosine transform; low cost design; inverse DCT architectures; time distribution scheme; coefficient matrix circuit; VC-1 standard; TSMC CMOS process; low-cost multistandard video transform core; size 0.18 mum; H.264 standard; multilevel factor share; distributed arithmetic; MPEG standard; hardware costs; 1D core

Subjects: Image and video coding; Integral transforms in numerical analysis; Digital arithmetic methods; Integral transforms in numerical analysis; Digital circuit design, modelling and testing; CMOS integrated circuits; Video signal processing

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      • 1. Huang, C.Y., Chen, L.F., Lai, Y.K.: ‘A high-speed 2-D transform architecture with unique kernel for multi-standard video application’. Proc. IEEE ISCAS, 2008, pp. 2124.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.3491
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