http://iet.metastore.ingenta.com
1887

Set/reset reference and parasitic matching scheme to speed up PCM read operation

Set/reset reference and parasitic matching scheme to speed up PCM read operation

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Three kinds of parameters are considered to speed up the read operation of phase change memory: bit line parasitic parameters, read transmission gate parasitic parameters and current mirror parasitic parameters. A set reference cell and a reset reference cell are used in the reference circuit. Simulated in 130 nm process, the read access time of 1-Mb phase change memory (PCM) is 6.7 ns. In Monte Carlo simulations, the worst read access time is 13.8 ns compared to conventional 85 ns.

References

    1. 1)
      • 1. Burr, G.W., Brightsky, M.J., Sebastian, A., et al: ‘Recent progress in phase-change memory technology’, J. Emerging Sel. Top. Circuits Syst., 2016, 99, pp. 117.
    2. 2)
    3. 3)
      • 3. Hanzawa, S., Kitai, N., Osada, K., et al: ‘A 512 kB embedded phase change memory with 416kB/s write throughput at 100 μA cell write current’. IEEE Int. Solid-state Circuits Conf., San Francisco, CA, USA, February 2007, pp. 474616.
    4. 4)
      • 4. Wang, Q., Li, X., Chen, H., et al: ‘Methods to speed up read operation in a 64mbit phase change memory chip’, Electron. Express, 2015, 12, (20), pp. 16.
    5. 5)
    6. 6)
      • 6. Tsuchida, K., Inaba, T., Fujita, K., et al: ‘A 64 Mb MRAM with clamped-reference and adequate-reference schemes’. IEEE Int. Solid-state Circuits Conf. Digest of Technical Papers, San Francisco, CA, USA, February 2010, pp. 258259.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.3132
Loading

Related content

content/journals/10.1049/el.2016.3132
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address