© The Institution of Engineering and Technology
Recently, multi-level cell (MLC) spin-transfer torque random access memories (STT-RAMs) are attracting great attentions as an alternative to static or dynamic random access memories. They have the benefits of capacity, but the penalties of performance, and power consumption caused by a complicated two- or three-phase access. An MLC STT-RAM controller that eliminates the MLC STT-RAM penalties for multimedia applications is proposed. The key ideas are frame-level data-to-memory mapping and frame-type aware frame assignment techniques that make a two- or three-phase access no longer required. Experimental results show that the proposed MLC STT-RAM controller achieves 56.1% higher memory performance, and 4.2% lower memory power consumption than the conventional controller for industrial multimedia applications.
References
-
-
1)
-
1. Chappert, C., Fert, A., Nguyen, V.D.F.: ‘The emergence of spin electronics in data storage’, Nat. Mater., 2007, 6, pp. 813–823, (doi: 10.1038/nmat2024).
-
2)
-
3. Sullivan, G.J., Ohm, J.-R., Han, W.-J., Wiegand, T.: ‘Overview of the high efficiency video coding (HEVC) standard’, Trans. Circuits Syst. Video Technol., 2012, 22, (12), pp. 1648–1667, .
-
3)
-
2. Ishigaki, T., Kawahara, T., Takemura, R., et al: ‘A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions’. Symp. on VLSI Technology, Honolulu, USA, June 2010, pp. 47–48, .
-
4)
-
5. Dong, X., Xu, C., Member, S., Xie, Y., Jouppi, N.P.: ‘NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012, 31, (7), pp. 994–1007 (doi: 10.1109/TCAD.2012.2185930).
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.2435
Related content
content/journals/10.1049/el.2016.2435
pub_keyword,iet_inspecKeyword,pub_concept
6
6