Your browser does not support JavaScript!

Multi-level cell STT-RAM controller for multimedia applications

Multi-level cell STT-RAM controller for multimedia applications

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Recently, multi-level cell (MLC) spin-transfer torque random access memories (STT-RAMs) are attracting great attentions as an alternative to static or dynamic random access memories. They have the benefits of capacity, but the penalties of performance, and power consumption caused by a complicated two- or three-phase access. An MLC STT-RAM controller that eliminates the MLC STT-RAM penalties for multimedia applications is proposed. The key ideas are frame-level data-to-memory mapping and frame-type aware frame assignment techniques that make a two- or three-phase access no longer required. Experimental results show that the proposed MLC STT-RAM controller achieves 56.1% higher memory performance, and 4.2% lower memory power consumption than the conventional controller for industrial multimedia applications.


    1. 1)
    2. 2)
      • 3. Sullivan, G.J., Ohm, J.-R., Han, W.-J., Wiegand, T.: ‘Overview of the high efficiency video coding (HEVC) standard’, Trans. Circuits Syst. Video Technol., 2012, 22, (12), pp. 16481667, doi: 10.1109/TCSVT.2012.2221191.
    3. 3)
      • 2. Ishigaki, T., Kawahara, T., Takemura, R., et al: ‘A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions’. Symp. on VLSI Technology, Honolulu, USA, June 2010, pp. 4748, doi: 10.1109/VLSIT.2010.5556126.
    4. 4)

Related content

This is a required field
Please enter a valid email address