Silicon photodetectors with triple p–n junctions in CMOS technology at 650- and 850-nm wavelengths

Silicon photodetectors with triple p–n junctions in CMOS technology at 650- and 850-nm wavelengths

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A triple p–n junction Si photodetector using 0.25-μm standard CMOS process at 650- and 850-nm wavelengths is presented and investigated. Triple p–n junctions are formed vertically by n+-implant/p-well (N+/HVPW), p-well/n+-buried layer (HVPW/NBL), and n+-buried layer/p-substrate (NBL/P-sub) junctions to attain a wavelength-dependent response. The responsivity and pulse response were characterised in different bias schemes. Measured photocurrents from HVPW/NBL and NBL/P-sub junctions under reverse biasing and a floating electrode on N+-HVPW showed the smallest FWHM values. The −3 dB bandwidth of 1.9 GHz converted from pulse measurement is the highest result ever reported in 654-nm wavelength using standard CMOS technology. The proposed triple p–n junction Si photodetector with bias schemes shows combined excellent performance in 650- and 850-nm wavelengths.


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      • 7. Iiyama1, K., Takamatsu, H., Maruyama, T.: ‘Silicon lateral avalanche photodiodes fabricated by standard 0.18 μm CMOS Process’. European Conf. on Optical Communication, 2009, pp. 12.
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