Efficient implementation of single event upset tolerant register comparison

Efficient implementation of single event upset tolerant register comparison

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In many applications, an incoming value is compared against one or more values stored in registers. To avoid data corruption, the registers are in some cases protected with a single error correction (SEC) code. Therefore, in a traditional implementation, SEC decoding would be done before the comparison. However, previous works have shown that it may be more efficient to compare the SEC encoded values directly using a distance one comparison. This distance one comparison prevents single bit errors from affecting the result of the comparison and is in many cases simpler than an SEC decoding plus a traditional comparison. It is shown that the use of single-error correction double error detection (SEC-DED) encoded registers enables a simplified distance one comparison that can further reduce the cost of implementing error protection for register comparison.


    1. 1)
      • 1. Kanekawa, N., Ibe, E.H., Suga, T., Uematsu, Y.: ‘Dependability in electronic systems: mitigation of hardware failures, soft errors, and electro-magnetic disturbances’ (Springer Verlag, New York, NY, USA, 2010), doi: 10.1007/978-1-4419-6715-2.
    2. 2)
    3. 3)
    4. 4)
      • 4. Pagiamtzis, K., Azizi, N.F., Najm, F.N.: ‘A soft-error tolerant content-addressable memory (CAM) using an error-correcting-match scheme’. Proc. of the IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, 10–13 September 2006, doi: 10.1109/CICC.2006.320887.

Related content

This is a required field
Please enter a valid email address