5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm² power area density in 180 nm CMOS process

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Author(s): H. Alsuraisry ¹ ; M.-H. Wu ² ; P.-S. Huang ² ; J.-H. Tsai ³ ; T.-W. Huang ²
- Affiliations: 1: Communications and Information Technology Research Institute, King Abdulaziz City for Science and Technology (KACST), Riyadh, Kingdom of Saudi Arabia ;
  2: Graduate Institute of Communication Engineering, National Taiwan University, Taipei 10617, Taiwan ;
  3: Department of Electrical Engineering, National Taiwan University, Taipei 10610, Taiwan
Source: Volume 52, Issue 15, 21 July 2016, p. 1338 – 1340
DOI: 10.1049/el.2016.1629 , Print ISSN 0013-5194, Online ISSN 1350-911X

A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode configuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm² in 0.263 mm² chip area to date.

References

1. 1)
  - 2. Haldi, P., Chowdhury, D., Reynaert, P., Liu, G., Niknejad, A.M.: ‘A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS’, IEEE J. Solid-State Circuits, 2008, 43, (5), pp. 1054–1063 (doi: 10.1109/JSSC.2008.920347).
2. 2)
  - 5. Yamashita, Y., Kanemoto, D., Kanaya, H., Pokharel, R.K., Yashida, K.: ‘A 5-GHz fully integrated CMOS class-E power amplifier using self-biasing technique with cascaded class-D drivers’. IEEE RFIT, Singapore, November 2012, pp. 237–239.
3. 3)
  - 4. Yamashita, Y., Kanemoto, D., Kanaya, H., Pokharel, R.K., Yoshida, K.: ‘A CMOS class-E power amplifier of 40-% PAE at 5 GHz for constant envelope modulation system’. IEEE SiRF, Austin, TX, January 2013, pp. 66–68.
4. 4)
  - 7. Solar, H., Berenguer, R., Adin, I., Alvarado, U., Cendoya, I.: ‘A fully integrated 26.5 dBm CMOS power amplifier for IEEE 802.11a WLAN standard with on-chip power inductors’. IEEE IMS, San Francisco, CA, June 2006, pp. 1875–1878.
5. 5)
  - 1. Ye, W., Ma, K., Yeo, K.S.: ‘A 2-to-6 GHz class-AB power amplifier with 28.4% PAE in 65 nm CMOS supporting 256QAM’. ISSCC Digest of Technical Papers, San Francisco, CA, February 2015, pp. 1–3.
6. 6)
  - 3. Wang, T.P., Ke, J.H., Chiang, C.Y.: ‘A high-Psat high-PAE fully-integrated 5.8-GHz power amplifier in 0.18-μm CMOS’. IEEE EDSSC, Tianjin, China, November 2011, pp. 1–2.
7. 7)
  - 6. Chen, J., Bhat, R., Krishnaswamy, H.: ‘A compact fully integrated high-efficiency 5 GHz stacked class-E PA in 65 nm CMOS based on transformer-based charging acceleration’. IEEE CSICS, La Jolla, CA, October 2012, pp. 1–4.
8. 8)
  - 8. Fathi, M., Su, D.K., Wooley, B.A.: ‘A 30.3 dBm 1.9 GHz-bandwidth 2 × 4-array stacked 5.3 GHz CMOS power amplifier’. ISSCC Digest of Technical Papers, San Francisco, CA, February 2013, pp. 88–89.
9. 9)
  - 9. Wang, H., Hashemi, H.: ‘A 0.5-6 GHz 25.6 dBm fully integrated digital power amplifier in 65-nm CMOS’. IEEE RFIC, Tampa, FL, June 2014, pp. 409–412.

5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process

References

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5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm² power area density in 180 nm CMOS process