access icon free High performance DRAM architecture with split row buffer

In dynamic random access memory (DRAM)-based main memory, access latency is a key performance metric. Commonly, the access latency is improved by employing row buffers that store the most recently accessed row data. However, if a new request tries to access a different row address from that in the row buffer, which is a row buffer conflict, the access latency is significantly increased. In a heterogeneous multi-core system, row buffer conflicts occur frequently because various types of processors with different access patterns share the main memory. A novel DRAM architecture that hides the latency penalty due to row buffer conflicts is proposed. The key idea is that read or write commands serviced during activate and precharge operations for different rows in the same bank are carried out by splitting the row buffer into two buffers. Experimental results show that the proposed DRAM architecture achieves up to 16% higher system performance for memory-intensive applications compared with a conventional DRAM architecture.

Inspec keywords: memory architecture; buffer storage; performance evaluation; DRAM chips; multiprocessing systems

Other keywords: split row buffer; precharge operations; system performance; performance metrics; memory-intensive applications; high performance DRAM architecture; activate operations; access latency improvement; write commands; read commands; heterogeneous multicore system; dynamic random access memory; latency penalty

Subjects: Storage system design; Memory circuits; Semiconductor storage; Multiprocessing systems; Performance evaluation and testing

References

    1. 1)
      • 2. JEDEC specification: ‘DDR3 SDRAM standard’. Available at http://www.jedec.org, accessed March 2016.
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    3. 3)
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.1111
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