access icon free SRAM cell with asymmetric pass-gate nMOSFETs for embedded memory applications

A novel asymmetric static RAM (SRAM) cell is fabricated on planar silicon-on-insulator CMOS technology, in which pass-gate (PG) transistors are asymmetric. Since lightly doped drain structure of PG transistors use only gate-to-source, this cell improves read stability by 43% when compared with the conventional SRAM 6T symmetric cell. Additionally, cell-leakage current reduces by 24% also due to the PG transistor gate-to-drain underlap design. Although it needs more current to write data to storage node, but no more voltage is needed based on measurements. The novel cell is still suitable for embedded memory.

Inspec keywords: leakage currents; CMOS memory circuits; integrated circuit design; embedded systems; circuit stability; SRAM chips; silicon-on-insulator

Other keywords: SRAM cell; asymmetric static RAM cell; asymmetric pass-gate nMOSFET; planar silicon-on-insulator CMOS technology; pass-gate transistors; embedded memory applications; cell-leakage current reduction; read stability improvement; PG transistor gate-to-drain underlap design; lightly doped drain structure

Subjects: Semiconductor storage; CMOS integrated circuits; Digital circuit design, modelling and testing; Memory circuits

http://iet.metastore.ingenta.com/content/journals/10.1049/el.2016.0938
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content/journals/10.1049/el.2016.0938
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