An inverted bit-line sense amplifier (BLSA) equipped with offset compensation capability for low-power DRAM applications is proposed. The sequential operation of the inverted BLSA allows us to eliminate the edge dummy array in an open bit-line structure resulting in 1.7% less total chip area despite of 10% area penalty of the proposed BLSA occupied by extra switches. For 8-Gb DRAM in 20-nm class technology, the read failure induced by Vth variability is completely removed due to the offset cancellation. The proposed BLSA maintains the gradual increase of the sensing delay when decreasing the power supply down to 0.6 V, while intrinsic read fail prevails below 0.9 V with the conventional one.