access icon free Improving graphene non-volatile memory using self-aligned gate

As the scale of graphene-based non-volatile memory is reduced, the ratio of access resistance R A to total channel resistance R TOT is increased. To investigate the effect of the R A on I–V characteristics, we fabricated devices with various access lengths L A and self-aligned structure. Proposed structure using self-aligned gate minimises L A, and thereby improves the drain current, ‘on/off’ current ratio I ON/I OFF and transfer characteristics. In proposed structure, ‘off’ current is increased from 0.16 to 0.28 mA because R TOT was reduced; ‘on’ current increased from 0.35 to 0.72 mA, but I ON/I OFF increased from 2.18 to 2.57. Proposed structure also had larger memory window (8.5 V) than did conventional devices (6.7 V).

Inspec keywords: graphene; random-access storage; graphene devices

Other keywords: current 0.16 mA to 0.28 mA; self-aligned gate structure; graphene nonvolatile memory; voltage 8.5 V; transfer characteristics; I-V characteristics; drain current; C; current 0.35 mA to 0.72 mA; voltage 6.7 V; channel resistance

Subjects: Semiconductor storage; Memory circuits; Fullerene, nanotube and related devices

http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.4274
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content/journals/10.1049/el.2015.4274
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