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9-bit time–digital-converter-assisted compressive-sensing analogue–digital-converter with 4 GS/s equivalent speed

9-bit time–digital-converter-assisted compressive-sensing analogue–digital-converter with 4 GS/s equivalent speed

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A novel 9-bit time–digital-converter (TDC)-assisted analogue–digital-converter (ADC) supporting energy-efficient high-speed compressive-sensing (CS) operation is presented. With a voltage–time-converter serving as the cross-domain residue conveyer, the proposed two-stage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC front-end and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.

References

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      • 8. Yousry, R., Chen, M-S., Chang, M-C., et al: ‘An architecture-reconfigurable 3b-to-7b 4 GS/s-to-1.5 GS/s ADC using subtractor interleaving’. 2013 IEEE Asian Solid-State Circuits Conf., Singapore, November 2013, pp. 285288.
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      • 6. Liscidini, A., Vercesi, L., Castello, R.: ‘Time to digital converter based on a 2-dimensions Vernier architecture’. 2009 IEEE Custom Integrated Circuits Conf., San Jose, USA, September 2009, pp. 4548.
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