Novel two-transistor embedded memory – floating body gate cell – is implemented on planar SOI CMOS technology without adding extra masks. Since channel current is designed for memory cell write operations, this cell demonstrates ultra-fast write speed which is comparable with static RAM cell. The decoupled write and read structure ensures small operation power consumption and avoid false read. The low operation voltages of this cell lead to the excellent endurance performance. In addition, retention time is greatly enhanced due to the gate-to-drain underlap design.