access icon free Floating body gate cell with fast write speed for embedded memory applications

Novel two-transistor embedded memory – floating body gate cell – is implemented on planar SOI CMOS technology without adding extra masks. Since channel current is designed for memory cell write operations, this cell demonstrates ultra-fast write speed which is comparable with static RAM cell. The decoupled write and read structure ensures small operation power consumption and avoid false read. The low operation voltages of this cell lead to the excellent endurance performance. In addition, retention time is greatly enhanced due to the gate-to-drain underlap design.

Inspec keywords: performance evaluation; silicon-on-insulator; integrated circuit design; CMOS memory circuits; low-power electronics; embedded systems

Other keywords: low operation voltages; memory cell write operations; decoupled write and read structure; planar SOI CMOS technology; retention time enhancement; gate-to-drain underlap design; ultra-fast write speed; channel current; two-transistor embedded memory; floating body gate cell; small operation power consumption; embedded memory applications

Subjects: Digital circuit design, modelling and testing; Performance evaluation and testing; Semiconductor storage; Memory circuits; CMOS integrated circuits

http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.3714
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content/journals/10.1049/el.2015.3714
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