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Continuous-time digital filtering analogue-to-digital converter

Continuous-time digital filtering analogue-to-digital converter

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Despite their alias-free operation, continuous time ADCs can have their power consumption overwhelmed when presented out-of-band, high frequency, high amplitude signals. A new continuous time ADC architecture which, thanks to its embedded low-pass filter transfer function is proposed, enables a power efficient quantisation in the presence of such signals. Moreover, the half-digital nature of this approach simplifies the implementation of the proposed system compared to a standard filter-first solution.

References

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      • 1. Weltin-Wu, C., Tsividis, Y.: ‘An event-driven, alias-free ADC with signal-dependent resolution’. Symp. on VLSI Circuits, June 2012, pp. 2829.
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      • 5. Harishchandra, V.M., Laxminidhi, T.: ‘0.5 V, 36 μW GmC Butterworth low pass filter in 0.18 μm CMOS process’. Asia Symp. on Quality Electronic Design, July 2012, pp. 8285.
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      • 4. Sosio, M., Liscidini, A., Castello, R., De Bernardinis, E.: ‘A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC’. European Solid States Circuit Conf., September 2011, pp. 391394.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.3204
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