© The Institution of Engineering and Technology
Technology scaling results in that, soft errors, due to radiation-induced single event double-upset (SEDU) that affects double nodes through charge sharing, become a prominent concern in nanoscale CMOS technology. Existing hardened schemes suffer from being not fully SEDU-immune, or perform with too large cost penalties regarding propagation delay, silicon area, and power dissipation. A novel high-performance, low-cost, and fully SEDU-immune latch, referred to as HSMUF, is presented to tolerate SEDU when any arbitrary combination pair of nodes is affected by a particle striking. The latch mainly consists of a clock gating-based triple path DICE and a multiple-input Muller C-element. Simulation results demonstrate the SEDU-immunity and a 99.73% area–power–delay product saving for the HSMUF latch, compared with the SEDU fully immune DNCS-SEUT latch.
References
-
-
1)
-
7. Ramin, R., Mahmoud, T., Mahdi, F.: ‘Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations’, J. Circuits Syst. Comput., 2015, 24, (1), pp. 1550007–1550037 (doi: 10.1142/S0218126615500073).
-
2)
-
4. Mitra, S., Zhang, M., Seifert, N., Mak, T.M., Kim, K.S.: ‘Built-in soft error resilience for robust system design’. IEEE Int. Conf. on Integrated Circuit Design and Technology, Austin, TX, USA, June 2007, pp. 1–6.
-
3)
-
6. Blum, D., Delgado-Frias, J.: ‘Schemes for eliminating transient width clock overhead from set-tolerant memory-based systems’, IEEE Trans. Nucl. Sci., 2006, 53, (3), pp. 1564–1573 (doi: 10.1109/TNS.2006.874496).
-
4)
-
8. Katsarou, K., Tsiatouhas, Y.: ‘Soft error interception latch: double node charge sharing SEU tolerant design’, Electron. Lett., 2015, 51, (4), pp. 330–332 (doi: 10.1049/el.2014.4374).
-
5)
-
3. Fazeli, M., Miremadi, S., Ejlali, A., Patooghy, A.: ‘Low energy single event upset/single event transient-tolerant latch for deep submicron technologies’, IET Comput. Digit. Tech., 2009, 3, (3), pp. 289–303 (doi: 10.1049/iet-cdt.2008.0099).
-
6)
-
2. Calin, T., Nicolaidis, M., Velazco, R.: ‘Upset hardened memory design for submicron CMOS technology’, IEEE Trans. Nucl. Sci., 1996, 43, (6), pp. 2874–2878 (doi: 10.1109/23.556880).
-
7)
-
1. Ferlet-Cavrois, V., Massengill, L., Gouker, P.: ‘Single event transients in digital CMOS – a review’, IEEE Trans. Nucl. Sci., 2013, 60, (3), pp. 1767–1790 (doi: 10.1109/TNS.2013.2255624).
-
8)
-
5. Black, J., Dodd, P., Warren, K.: ‘Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction’, IEEE Trans. Nucl. Sci., 2013, 60, (3), pp. 1836–1851 (doi: 10.1109/TNS.2013.2260357).
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.3020
Related content
content/journals/10.1049/el.2015.3020
pub_keyword,iet_inspecKeyword,pub_concept
6
6