access icon free High-performance, low-cost, and highly reliable radiation hardened latch design

Technology scaling results in that, soft errors, due to radiation-induced single event double-upset (SEDU) that affects double nodes through charge sharing, become a prominent concern in nanoscale CMOS technology. Existing hardened schemes suffer from being not fully SEDU-immune, or perform with too large cost penalties regarding propagation delay, silicon area, and power dissipation. A novel high-performance, low-cost, and fully SEDU-immune latch, referred to as HSMUF, is presented to tolerate SEDU when any arbitrary combination pair of nodes is affected by a particle striking. The latch mainly consists of a clock gating-based triple path DICE and a multiple-input Muller C-element. Simulation results demonstrate the SEDU-immunity and a 99.73% area–power–delay product saving for the HSMUF latch, compared with the SEDU fully immune DNCS-SEUT latch.

Inspec keywords: flip-flops; logic design; radiation hardening (electronics)

Other keywords: clock gating-based triple path DICE; power dissipation; multiple-input Muller C-element; HSMUF latch; SEDU-immunity; technology scaling results; double nodes; propagation delay; silicon area; soft errors; charge sharing; nanoscale CMOS technology; SEDU-immune latch; particle striking; radiation-induced single event double-upset

Subjects: Radiation effects (semiconductor technology); Logic design methods; Logic circuits; Logic and switching circuits; Digital circuit design, modelling and testing

References

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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.3020
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