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Two-transistor and two-magnetic-tunnel-junction multi-level cell structured spin-transfer torque magnetic random access memory with optimisations on power and reliability

Two-transistor and two-magnetic-tunnel-junction multi-level cell structured spin-transfer torque magnetic random access memory with optimisations on power and reliability

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A two-transistor and two-magnetic-tunnel-junction (MTJ) multi-level cell (MLC) structure of spin-transfer torque magnetic random access memory (STT-RAM) is proposed. Compared with the conventional one-transistor and two-magnetic-tunnel-junction MLC STT-RAMs, by adding an extra access transistor and adjusting the connection of the two MTJs, the extra write power consumption on the soft bit MTJ can be reduced, which will also have a benefit to the lifetime of the soft bit. Specifically, the simulation results show that more than 75% write power consumption on the soft bit can be wiped out, and the area cost caused by the extra access transistor is negligible.

References

    1. 1)
      • 1. Zhang, Y., Zhao, W., Klein, J.O., Kang, W.: ‘Multi-level cell spin transfer torque MRAM based on stochastic switching’. IEEE Int. Conf. on Nanotechnology (IEEE-NANO), Beijing, China, August 2013, pp. 233236, doi: 10.1109/NANO.2013.6720849.
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      • 2. Bi, X., Mao, M., Wang, D., Li, H.: ‘Unleashing the potential of MLC STT-RAM caches’. IEEE/ACM Int. Conf. on Computer-Aided Design, San Jose, CA, USA, November 2013, pp. 429436, doi: 10.1109/ICCAD.2013.6691153.
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      • 3. Ishigaki, T., Kawahara, T., Takemura, R.: ‘A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions’. 2010 Symp. on VLSI Technology, Honolulu, June 2010, pp. 4748, doi: 10.1109/VLSIT.2010.5556126.
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      • 4. Panagopoulos, G., Augustine, C., Roy, K.: ‘Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation’. IEEE Device Research Conf. (DRC), Santa Barbara, CA, June 2011, pp. 125126, doi: 10.1109/DRC.2011.5994447.
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      • 5. Kim, Y., Gupta, S.K., Park, S.P.: ‘Write-optimized reliable design of STT MRAM’. ACM/IEEE Int. Symp. on Low Power Electronics and Design, Redondo Beach, July 2012, pp. 38.
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      • 6. Zhang, Y., Zhang, L., Wen, W., Sun, G., Chen, Y.: ‘Multi-level cell STT-RAM: is it realistic or just a dream’. ACM Int. Conf. on Computer-Aided Design, San Jose, CA, November 2012, pp. 526532.
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