access icon free MFSFET two-bit 1T1C DRAM memory design and empirical data

Operation of the 1-transistor, 1-capacitor dynamic random access memory cell that allows for two-bit operation, double the typical storage capacity, is explored. By using a metal-ferroelectric-semiconductor field-effect transistor, a second bit is captured in the ferroelectric layer polarisation resulting from negative and positive polarisation states. As a result, new modes of operation are created giving non-volatile, long-term storage as well as decreased power consumption and radiation hardening. A typical write and read operating cycle is outlined in-depth and used to verify operation indicating four distinct states representing the two bits. The resulting empirical data gives a comprehensive presentation of the read cycle of the memory cell. Methods for determining the polarisation state of the transistor are also explored and used to determine the average value for measured channel resistance using three types of transistors, each having different channel width and length.

Inspec keywords: ferroelectric semiconductors; radiation hardening (electronics); DRAM chips; field effect transistors; ferroelectric capacitors

Other keywords: radiation hardening; positive polarisation; negative polarisation; ferroelectric layer polarisation; nonvolatile long-term storage; MFSFET two-bit 1T1C DRAM memory design; channel resistance measurement; 1-transistor 1-capacitor dynamic random access memory cell; word length 2 bit; write and read operating cycle; metal-ferroelectric-semiconductor field-effect transistor; power consumption

Subjects: Piezoelectric and ferroelectric materials; Semiconductor storage; Other field effect devices; Ferroelectric devices; Radiation effects (semiconductor technology); Capacitors; Memory circuits

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