© The Institution of Engineering and Technology
A new architecture to multiply signals with timemode representations is proposed. The exponential relationship between voltage and time in an RC circuit is utilised to implement the timemode logarithmic and exponential functions needed to realise a timemode analogue of the translinear principle. The addition of timemode variables is achieved through the natural progression of time equal to the sum of the input times. By combining these two techniques, an analogue multiplier can be implemented almost exclusively with passive circuits and digital primitives. Therefore, the circuit performance could benefit from CMOS scaling trends. The architecture is described, and simulation results are presented for an operational circuit implementing this approach.
References


1)

1. Chakrabartty, S., Cauwenberghs, G.: ‘Submicrowatt analog VLSI trainable pattern classifier’, IEEE J. SolidState Circuits, 2007, 42, (5), pp. 1169–1179 (doi: 10.1109/JSSC.2007.894803).

2)

2. Loeliger, H.A., Lustenberger, F., Helfenstein, M., et al: ‘Probability propagation and decoding in analog VLSI’, IEEE Trans. Inf. Theory, 2001, 47, (2), pp. 837–843 (doi: 10.1109/18.910594).

3)

3. Ravinuthula, V., Garg, V., Harris, J.G., et al: ‘Timemode circuits for analog computation’, Int. J. Circuit Theory Appl., 2009, 37, pp. 631–659 (doi: 10.1002/cta.488).

4)

4. Miyashita, D., Yamaki, R., Hashiyoshi, K., et al: ‘An LDPC decoder with timedomain analog and digital mixedsignal processing’, IEEE J. SolidState Circuits, 2014, 49, (1), pp. 73–81 (doi: 10.1109/JSSC.2013.2284363).

5)

5. Gilbert, B.: ‘Translinear circuits: a proposed classification’, Electron. Lett., 1975, 11, pp. 14–16 (doi: 10.1049/el:19750011).

6)

6. D'Angelo, R., Sonkusale, S.: ‘A timemode translinear principle for implementing analog multiplication’. 2014 IEEE Int. Symp. on Circuits and Systems (ISCAS), Melbourne, Australia, June2014, pp. 73–76.

7)

3. Taillefer, C., Roberts, G.: ‘Delta sigma A/D conversion via timemode signal processing’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2009, 56, (9), pp. 1908–1920 (doi: 10.1109/TCSI.2008.2010144).
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.2235
Related content
content/journals/10.1049/el.2015.2235
pub_keyword,iet_inspecKeyword,pub_concept
6
6