access icon free VLSI implementation of fractional motion estimation interpolation for high efficiency video coding

© The Institution of Engineering and Technology
Received 23/04/2015, Published 03/07/2015

Interpolation plays a key role in the fractional motion estimation (FME) of video encoders. A hardware implementation of a FME interpolator is presented for high efficiency video coding. The proposed interpolator processes each 8 × 8 block in a pipelined manner with efficiently shared finite impulse response filters to improve the performance while reducing gate counts. Implementation results show that the proposed design leads to fewer execution cycles with a small silicon area compared with conventional designs.

Inspec keywords: video coding; VLSI; interpolation; motion estimation; FIR filters

Other keywords: VLSI implementation; hardware implementation; finite impulse response filters; HEVC; FIR filters; video encoders; fractional motion estimation interpolation; high efficiency video coding; FME interpolator

Subjects: Video signal processing; Codecs, coders and decoders; Interpolation and function approximation (numerical analysis); Image and video coding; Computer vision and image processing techniques; Interpolation and function approximation (numerical analysis); Filtering methods in signal processing; Semiconductor integrated circuits

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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.1412
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