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DEC-cache: dynamically electing candidate cache for low power utilising hearing policy

DEC-cache: dynamically electing candidate cache for low power utilising hearing policy

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On-chip cache memory is one of the largest power consumers in modern microprocessors. A dynamic way prediction scheme utilising a hearing policy is proposed for a low-power level-one cache design that handles power limit issues. The high prediction accuracy of the dynamically electing candidate (DEC)-cache helps to prevent large miss penalties. Owing to the high prediction accuracy, the experimental results show that the DEC-cache structure improves the energy-delay product by 26% compared with the existing buffered dual-mode cache.

References

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      • 5. Linley, G.: ‘Sandy Bridge spans generations’. Microprocessor Report, Mountain View, CA, USA, 27 September2010.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.1153
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