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Efficient replica bitline technique for variation-tolerant timing generation scheme of SRAM sense amplifiers

Efficient replica bitline technique for variation-tolerant timing generation scheme of SRAM sense amplifiers

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An efficient replica bitline (RBL) technique for reducing the variation of sense amplifier enable (SAE) timing is proposed. Both RBLs and four-fold replica cells compared with the conventional RBL technique are utilised to favour the desired operations. Simulation results show that the standard deviation of SAE can be suppressed by 44.25% and the cycle time is also reduced by ∼30% at a 0.8 V supply voltage in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that of the conventional RBL scheme.

References

    1. 1)
      • 1. Arslan, U., et al: ‘Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines’. Proc. of IEEE Custom Integrated Circuits Conf., (CICC2008), San Jose, CA, USA, September 2008, pp. 415418.
    2. 2)
    3. 3)
      • 3. Komatsu, S., et al: ‘A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation’. Proc. of IEEE Custom Integrated Circuits Conf., (CICC2009), San Jose, CA, USA, September 2009, pp. 701704.
    4. 4)
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    6. 6)
      • 6. Yi, L., et al: ‘An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing’, IEICE Electron. Express, 2014, 11, (3), pp. 16.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2015.0574
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