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access icon free 237 Gbit/s unrolled hardware polar decoder

 A new architecture for a polar decoder using a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel fully unrolled, deeply pipelined architecture is capable of achieving a coded throughput of over 237 Gbit/s for a (1024, 512) polar code implemented using a field-programmable gate array. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.

References

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      • 6. Dizdar, O., Arıkan, E.: ‘A high-throughput energy-efficient implementation of successive-cancellation decoder for polar codes using combinational logic’. CoRR, December 2014, vol. abs/1412.3829, Available at http://www.arxiv.org/abs/1412.3829.
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      • 7. Wong, H., Betz, V., Rose, J.: ‘Comparing FPGA vs. custom CMOS and the impact on processor microarchitecture’. ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays, Monterey, CA, USA, March 2011, pp. 514.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2014.4432
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content/journals/10.1049/el.2014.4432
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