access icon free Soft error interception latch: double node charge sharing SEU tolerant design

As technology scales down, soft errors, because of single event upsets (SEUs) that affect multiple nodes (through multiple node charge sharing), become a serious concern in nanometre technology integrated circuits. Existing radiation hardening techniques provide partial or no immunity when more than one node are affected. A new latch topology is presented that guarantees soft error tolerance when a single node or any arbitrary combination of node pairs is affected by an SEU. The proposed scheme exploits a positive feedback loop which consists of C-elements. Simulation results validate the efficiency of the new design over existing soft error hardening techniques such as BISER, FERST and TPDICE.

Inspec keywords: logic design; radiation hardening (electronics); flip-flops; nanoelectronics

Other keywords: soft error hardening techniques; latch topology; TPDICE; positive feedback loop; radiation hardening techniques; nanometre technology integrated circuits; C-elements; single event upsets; multiple node charge sharing; soft error tolerance; FERST; double node charge sharing SEU tolerant design; soft error interception latch; BISER

Subjects: Logic circuits; Logic and switching circuits; Radiation effects (semiconductor technology); Logic design methods; Digital circuit design, modelling and testing

References

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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2014.4374
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