Soft error interception latch: double node charge sharing SEU tolerant design

Soft error interception latch: double node charge sharing SEU tolerant design

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As technology scales down, soft errors, because of single event upsets (SEUs) that affect multiple nodes (through multiple node charge sharing), become a serious concern in nanometre technology integrated circuits. Existing radiation hardening techniques provide partial or no immunity when more than one node are affected. A new latch topology is presented that guarantees soft error tolerance when a single node or any arbitrary combination of node pairs is affected by an SEU. The proposed scheme exploits a positive feedback loop which consists of C-elements. Simulation results validate the efficiency of the new design over existing soft error hardening techniques such as BISER, FERST and TPDICE.


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      • 4. Mitra, S., Zhang, M., Seifert, N., Mak, T.M., Kim, K.S.: ‘Built-in soft error resilience for robust system design’. IEEE Int. Conf. on Integrated Circuit Design and Technology, Austin, TX, USA, June 2007, pp. 16.
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