Efficient error detection in multiple way tables

Efficient error detection in multiple way tables

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Multiple way tables in which items can be placed on several buckets are used in many computing applications. Some examples are cache memories and multiple hash tables structures. In most cases, the items are stored in electronic memories that are prone to soft errors that can corrupt the stored items. To avoid data corruption, memories can be protected with a parity bit or with an error correction code. It is shown that most single bit errors can be detected in multiple way tables without adding a parity bit. This can be done by placing the items in a predetermined order in the multiple ways of the table.


    1. 1)
      • 1. Hennessy, J.L., Patterson, D.A.: ‘Computer architecture: a quantitative approach’ (Morgan Kaufmann, San Francisco, CA, USA, 2012).
    2. 2)
      • 2. Kirsch, A., Mitzenmacher, M., Varghese, G.: ‘Hash-based techniques for high-speed packet processing’, in Cormode, G., Thottan, M. (Eds.): ‘Algorithms for next generation networks’ (Springer, London, 2010), pp. 181218.
    3. 3)
      • 3. Kanekawa, N., Ibe, E.H., Suga, T., Uematsu, Y.: ‘Dependability in electronic systems: mitigation of hardware failures, soft errors, and electro-magnetic disturbances’ (Springer Verlag, New York, NY, USA, 2010).
    4. 4)
    5. 5)
      • 5. Gherman, V., Evain, S., Seymour, N., Bonhomme, Y.: ‘Generalized parity-check matrices for SEC-DED codes with fixed parity’. IEEE 17th Int. On-Line Testing Symp. (IOLTS), Athens, Greece, July 2011, pp. 198201.
    6. 6)
      • 6. Zhou, D., Fan, B., Lim, H., Kaminsky, M., Andersen, D.G.: ‘Scalable, high performance Ethernet forwarding with CuckooSwitch’. ACM CoNEXT, Santa Barbara, CA, USA, December 2013.

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