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Low-cost memory data scheduling method for reconfigurable FFT bit-reversal circuits

Low-cost memory data scheduling method for reconfigurable FFT bit-reversal circuits

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A low-cost memory data scheduling method based on two N/2-depth single-port memories is proposed for reconfigurable fast Fourier transform (FFT) bit-reversed data reordering tasks. To make single-port memories have the equivalent ability to read and write data simultaneously, two types of read and write address generation methods are proposed. Based on the proposed data scheduling method, the bit-reversal circuits are designed for continuous data reordering tasks. The proposed bit-reversal design is implemented for a maximum 8 k flexible length FFT processor. Compared with the other two conventional methods, the proposed bit-reversal method can reduce memory area cost by 53.8 and 46.1%, respectively.

References

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      • 3. Chakraborty, T.S., Chakrabarti, S.: ‘On output reorder buffer design of bit reversed pipelined continuous data FFT architecture’. IEEE Asia Pacific Conf. on Circuits and System, Macao, China, December, 2008, pp. 11321135.
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      • 4. Kristensen, F., Nilsson, P., Olsson, A.: ‘Reduced transceiver-delay for OFDM systems’. IEEE Vehicular Technical Conf., Los Angeles, CA, USA, September, 2004, pp. 12421245.
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