access icon free Simultaneous process self-calibration method using TDC for 3D DDR4 DRAM

Three-dimensional (3D) dynamic random-access memory (DRAM) with TSVs has been proposed due to continuous demands for low-power and high-density memory without IO loading limitation. However, the process difference among the stacked dies causes the timing mismatch of internal signals. To remove signal confliction and reduce signal skews among the stacked dies, the simultaneous process self-calibration scheme is proposed. The stacked dies using the proposed scheme detect the slowest signal among the stacked dies and internal signals are aligned with the slowest signal at the same time. The time for aligned operation is within one read loop and the scheme is turned off after calibration to reduce additional standby current. The 3D double-data rate 4 (DDR4) DRAM using the proposed scheme is operated over 2133 Mbit/s at 1.2 V.

Inspec keywords: integrated circuit design; three-dimensional integrated circuits; DRAM chips; low-power electronics; time-digital conversion

Other keywords: voltage 1.2 V; 3D DDR4 DRAM; TDC; time-to-digital converter; high density memory; slowest signal detection; self-calibration method; three dimensional dynamic random access memory; 3D double data rate 4 DRAM; low power electronics; TSV

Subjects: Digital circuit design, modelling and testing; Semiconductor storage; A/D and D/A convertors; A/D and D/A convertors; Logic design methods; Semiconductor integrated circuit design, layout, modelling and testing; Memory circuits

References

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      • 2. Kim, J., Oh, C., Lee, H., Lee, D., Hwang, H., Hwang, S., Na, B., Moon, J., Kim, J., Park, H., Ryu, J., Park, K., Kang, S., Kim, S., Kim, H., Bang, J., Cho, H., Jang, M., Han, C., Lee, J., Kyung, K., Choi, J., Jun, Y.: ‘A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 × 128 I/Os using TSV-based stacking’. ISSCC, 2011, pp. 496497.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2014.1595
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