http://iet.metastore.ingenta.com
1887

DECO: DIMM controller efficient for ECC operations

DECO: DIMM controller efficient for ECC operations

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

An error-correcting code (ECC) immune to bit errors can make memory performance severely degraded since incomplete-word ECC write requests lead to inefficient operations on a dual in-line memory module (DIMM). A DIMM controller efficient for such ECC operations is proposed. The key idea is that read-to-write and write-to-read operations caused by incomplete-word ECC write requests are split into independent read and write operations, and then the read and write operations are individually scheduled under data coherence constraints. Experimental results show that the proposed DIMM controller achieves 11% shorter memory latency, and 9.3% higher memory utilisation, on average, than the latest conventional DIMM controller in industrial multimedia applications. Moreover, it achieves up to 2.1 times higher memory performance on synthetic benchmarks.

References

    1. 1)
      • 1. Bogatin, E.: ‘Signal Integrity: Simplified’ (Prentice-Hall, Upper Saddle River, NJ, USA, 2003).
    2. 2)
      • 2. JEDEC specifications: ‘DDR 1, 2, and 3 SDRAM Standard’. Available at http://www.jedec.org, accessed April 2014.
    3. 3)
    4. 4)
      • 4. Sonics MemMax specification: ‘MemMax DRAM system’. Available at http://sonicsinc.com, accessed April 2014.
    5. 5)
    6. 6)
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2014.1135
Loading

Related content

content/journals/10.1049/el.2014.1135
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address