access icon free Comparison of Verilog-A compact modelling strategies for spintronic devices

Magnetic random access memory based on magnetic tunnel junctions (MTJs) is among the most attractive technologies of emerging non-volatile memories. However, the integration of spin-based devices in integrated circuits is still hindered by a lack of established standard electrical simulator models. Many of such models have been proposed during the past decade which can be classified into two categories: the first ones are based on the physical Landau-Lifshitz-Gilbert (LLG) equation describing real-time MTJ magnetic switching dynamics; the second one uses analytical expressions for switching thresholds derived from the LLG equation. The aim of this reported work was to investigate for the first time the capability of each strategy to fulfil the need of industrial standard electrical simulation tools and pave the path towards a standard industrial model. Multi-simulator compatibility, efficient runtime, accuracy and reliability are the three main assets of a device model. It is shown that using the Cadence® tools suite with the Spectre® simulator, the LLG modelling strategy overcomes the analytical approach in terms of accuracy and speed with a 7× faster runtime. Both models require nearly the same hardware memory resources.

Inspec keywords: magnetoelectronics; hardware description languages; random-access storage; magnetic tunnelling; MRAM devices; integrated circuit reliability; integrated circuit modelling

Other keywords: MRAM; magnetic tunnel junctions; nonvolatile memories; Landau–Lifshitz–Gilbert equation; magnetic random access memory; Spectre® simulator; magnetic switching dynamics; Verilog-A compact modelling; multisimulator compatibility; spintronic devices; Cadence® tools suite

Subjects: Magneto-acoustic, magnetoresistive, magnetostrictive and magnetostatic wave devices; Reliability; Storage on stationary magnetic media; Memory circuits; Digital circuit design, modelling and testing

References

    1. 1)
      • 4. Mierzwinsk, M., Halloran, P.O., Troyanovsky, B., Dutton, R.: ‘Changing the paradigm for compact model integration in circuit simulators using Verilog-A’. Tech. Proc. of 2003 Nanotechnology Conf. and Trade Show, Vol. 2, Chap. 7: Compact Modeling, San Francisco, CA, USA, February 2003, pp. 376379.
    2. 2)
      • 7. Jabeur, K., Di Pendina, G., Prenat, G., Buda-Prejbeanu, L.D., Dieny, B.: ‘Compact modeling of a magnetic tunnel junction based on spin orbit torque’, IEEE Trans. Magn., Doi (identifier): 10.1109/TMAG.2014.2305695.
    3. 3)
    4. 4)
    5. 5)
    6. 6)
      • 9. Depeyrot, G., Poullet, F., Dumas, B.: ‘Verilog-A compact model coding whitepaper’. Proc. Nanotech 2010, Anaheim, CA, USA, June 2010, Vol. 2, pp. 821824.
    7. 7)
    8. 8)
      • 8. Coram, G.J.: ‘How to (and how not to) write a compact model in Verilog-A’. Proc. 2004 IEEE Int. Behavioral Modeling and Simulation Conf. (BMAS 2004), San Jose, CA, USA, October 2004.
    9. 9)
      • 5. Jabeur, K., Prenat, G., Di Pendina, G., Buda Prejbeanu, L.D., Prejbeanu, I.L., Dieny, B.: ‘Compact model of a three-terminal MRAM device based on spin orbit torque switching’. Proc. of 2013 Semiconductor Conf., Dresden, Germany, September 2013.
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