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access icon free Four-channel self-compensating single-slope ADC for space environments

© The Institution of Engineering and Technology
Received 23/02/2014, Published 07/04/2014

A multichannel high-resolution single-slope analogue-to-digital converter (SS ADC) is presented that automatically compensates for process, voltage and temperature variations, as well as for radiation effects, in order to be used in extreme environmental conditions. The design combines an efficient implementation by using a feedback loop that ensures an inherently monotonic and very accurate ramp generation, with high levels of configurability in terms of resolution and conversion rate, as well as input voltage range. The SS ADC was designed in a standard 0.35 µm CMOS technology. Experimental measurements of the performance and stability against radiation and temperature are presented to verify the proposed approach.

Inspec keywords: CMOS digital integrated circuits; analogue-digital conversion; circuit feedback; space vehicle electronics

Other keywords: CMOS technology; multichannel high-resolution single-slope analogue-to-digital converter; process voltage and temperature variations; PVT variations; feedback loop; space environments; size 0.35 mum; ramp generation; 4-channel self-compensating single-slope ADC

Subjects: A/D and D/A convertors; CMOS integrated circuits; Space vehicle electronics; A/D and D/A convertors

References

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      • 5. Sordo-Ibanez, S., et al: ‘An adaptive approach to on-chip CMOS ramp generation for high resolution single-slope ADCs’. Proc. 2013 European Conf. on Circuit Theory and Design, Dresden, Germany, September 2013, pp. 1–4.
    2. 2)
      • 6. Ramos-Martos, J., et al: ‘Evaluation of the AMS 0.35 µm CMOS technology for use in space applications’. Proc. 2012 Analog and Mixed-Signal Integrated Circuits for Space Applications Workshop, Noordwijk, The Netherlands, August 2012.
    3. 3)
      • 4. Vergine, T., et al: ‘An automatic calibration circuit for 12-bits single-ramp A-to-D converter in LHC environments’. Proc. 2013 Conf. on Ph.D. Research in Microelectronics and Electronics, Villach, Austria, June 2013, pp. 45–48.
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      • 3. Osaki, Y., et al: ‘A low-power single-slope analog-to-digital converter with digital PVT calibration’. Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, Seville, Spain, December 2012, pp. 613–616.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2014.0664
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