© The Institution of Engineering and Technology
The method of quasi-delay-insensitive logic synthesis using look-up tables (LUTs) is described. It is shown that the dual-rail sum-of-minterm function hazard-free implementation can be done using a single LUT. Namely, instead of the conventional approach based on a DIMS representation where each minterm is implemented on a C-element, the whole sum-of-minterm function is mapped into the single C-element. For Boolean network implementation, it is proved that a fork with branches to different nodes is not required to be isochronic. It simplifies technological synthesis and allows using existing placement and routine methods and tools supposed for synchronous logic. Compared to the conventional approach, the method reduces significantly circuit complexity (in terms of the number of LUTs).
References
-
-
1)
-
2. Sparsø, E.J., Staunstrup, J., Dantzer-Sørensen, M.: ‘Design of delay insensitive circuits using multi-ring structures’. Proc. European Design Automation Conf. (EURO-DAC'92), Hamburg, Germany, September 1992, pp. 15–20.
-
2)
-
4. Smith, S.C., Di, J.: ‘Designing asynchronous circuits using NULL convention logic (NCL)’ (Morgan & Claypool, San Rafael, CA, USA, 2009), p. 96.
-
3)
-
11. Sentovich, E., et al: ‘SIS: a system for sequential circuit synthesis, electronic research laboratory memorandum’. , 1992, p. 45.
-
4)
-
5. Cortadella, J., Kondratyev, A., Lavagno, L., Sotiriou, C.P.: ‘Coping with the variability of combinational logic delays’. IEEE Int. Conf. Computer Design, San Jose, CA, USA, October 2004, pp. 505–508.
-
5)
-
10. Martin, A.J.: ‘The limitations to delay insensitivity in asynchronous circuits’. Sixth MIT Conf. Advanced Research in VLSI Processes, Cambridge, MA, USA, April 1990, pp. 263–277.
-
6)
-
1. Sparsø, E.J., Furber, S.: ‘Principles of asynchronous circuit design‘ (Kluwer Academic Publishers, Boston, MA, USA, 2001), p. 337.
-
7)
-
4. Smith, S.C., Di, J.: ‘Designing asynchronous circuits using NULL convention logic (NCL)’ (Morgan & Claypool, San Rafael, CA, USA, 2009), p. 96.
-
8)
-
11. Sentovich, E., et al: . , 1992, p. 45.
-
9)
-
5. Cortadella, J., Kondratyev, A., Lavagno, L., Sotiriou, C.P.: ‘Coping with the variability of combinational logic delays’. IEEE Int. Conf. Computer Design, San Jose, CA, USA, October 2004, pp. 505–508.
-
10)
-
10. Martin, A.J.: ‘The limitations to delay insensitivity in asynchronous circuits’. Sixth MIT Conf. Advanced Research in VLSI Processes, Cambridge, MA, USA, April 1990, pp. 263–277.
-
11)
-
8. Ho, Q.T., Rigaud, J.-B., Fesquet, L., Renaudin, M., Rolland, R.: ‘Implementing asynchronous circuits on LUT based FPGAs’. Proc. 12th Int. Conf. Field-Programmable Logic and Applications (FPL2002), Montpellier, France, September 2002, pp. 36–46.
-
12)
-
9. Lemberski, I., Fišer, P.: ‘Area and speed oriented implementations of asynchronous logic operating under strong constraints’. Proc. 13th Euromicro Conf. Digital Systems Design (DSD), Lille (France), 1–3 September 2010, pp. 155–162.
-
13)
-
2. Sparsø, E.J., Staunstrup, J., Dantzer-Sørensen, M.: ‘Design of delay insensitive circuits using multi-ring structures’. Proc. European Design Automation Conf. (EURO-DAC'92), Hamburg, Germany, September 1992, pp. 15–20.
-
14)
-
6. Lemberski, I., Fišer, P.: ‘Dual-rail asynchronous logic multi-level implementation’, Integr.VLSI J., Elsevier, 2014, 47, (1), pp. 148–159 (doi: 10.1016/j.vlsi.2013.02.002).
-
15)
-
7. Hauk, S., Burns, S., Borriello, G., Ebeling, C.: ‘An FPGA asynchronous circuits’, IEEE Design Test Comput., 1994, 11, (3), pp. 60–69 (doi: 10.1109/MDT.1994.303848).
-
16)
-
3. Nielsen, C.D.: ‘Evaluation of function block designs’. , Technical University of Denmark, Denmark, 1994, p. 43.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2014.0242
Related content
content/journals/10.1049/el.2014.0242
pub_keyword,iet_inspecKeyword,pub_concept
6
6