Improved design of high-frequency sequential decimal multipliers

Improved design of high-frequency sequential decimal multipliers

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Hardware implementation of decimal arithmetic operations has become a hot topic for research during the last decade. Among various operations, decimal multiplication is considered as one of the most complicated dyadic operations, which requires high-cost hardware implementation. Therefore, the processor industry has opted to use the sequential decimal multipliers to reduce the high cost of parallel architectures. However, the main drawback of iterative multipliers is their high latency. In this reported work, the focus has been on reducing the latency of decimal sequential multipliers while maintaining a low cost of area. Consequently, a high-frequency sequential decimal multiplier is proposed whose cycle time is reduced to the latency of a binary half-adder plus that of a decimal multiply-by-two operation, which overall is less than that of a decimal carry-save adder. The synthesis results reveal that the proposed sequential multiplier works with a higher clock frequency than the fastest previous decimal multiplier which in turn leads to overall latency advantage.


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