access icon free High reliability sensing circuit for deep submicron spin transfer torque magnetic random access memory

© The Institution of Engineering and Technology
Received 12/07/2013, Published
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A high reliability offset-tolerant sensing circuit is presented for deep submicron spin transfer torque magnetic tunnel junction (STT-MTJ) memory. This circuit, using a triple-stage sensing operation, is able to tolerate the increased process variations as technology scales down to the deep submicron nodes, thus improving significantly the sensing margin. Meanwhile, it clamps the bit-line voltage to a predefined small bias voltage to avoid any read disturbance during the sensing operations. By using the STMicroelectronics CMOS 40 nm design kit and a precise STT-MTJ compact model, Monte Carlo simulations have been carried out to evaluate its sensing performance.

Inspec keywords: semiconductor device reliability; magnetic tunnelling; random-access storage; CMOS memory circuits; Monte Carlo methods

Other keywords: deep submicron spin transfer torque magnetic random access memory; predefined small bias voltage; STMicroelectronics CMOS design kit; high reliability sensing circuit; deep submicron nodes; Monte Carlo simulations; triple-stage sensing operation; STT-MTJ compact model; bit-line voltage

Subjects: Reliability; Memory circuits; Monte Carlo methods; Monte Carlo methods; CMOS integrated circuits; Semiconductor storage

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