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access icon free Continuous-flow variable-length memoryless linear regression architecture

© The Institution of Engineering and Technology
Received 25/06/2013, Published

A pipelined circuit to calculate linear regression is presented. The proposed circuit has the advantages that it can process a continuous flow of data, it does not need memory to store the input samples and supports variable length that can be reconfigured in run time. The circuit is efficient in area, as it consists of a small number of adders, multipliers and dividers. These features make it very suitable for real-time applications, as well as for calculating the linear regression of a large number of samples.

Inspec keywords: logic design; multiplying circuits; dividing circuits; adders; regression analysis

Other keywords: pipelined circuit; dividers; multipliers; adders; continuous-flow variable-length memoryless linear regression architecture

Subjects: Logic design methods; Digital circuit design, modelling and testing; Logic and switching circuits; Logic circuits

References

    1. 1)
      • 2. Kulkarni, J., Sawant, A., Inamdar, V.: ‘Database processing by linear regression on GPU using CUDA’. Proc. Int. Conf. Signal Processing Communication and Computer and Networking Technologies, Thuckalay, India, July 2011, pp. 20–23.
    2. 2)
      • 8. Royer, P., Sánchez, M., López-Vallejo, M., López, C.A.: ‘Area-efficient linear regression architecture for real-time signal processing on FPGAs’. Proc. Conf. Design of Circuits and Integrated Systems, Albufeira, Portugal, November 2011.
    3. 3)
      • 9. Washizawa, T.: ‘Regression analysis apparatus and method’, US Patent 20070288199, 2007.
    4. 4)
      • 1. Draper, N., Smith, H.: ‘Applied regression analysis’ (John Willey and Sons, 1980).
    5. 5)
      • 5. Grajal, J., Yeste-Ojeda, O., Sánchez, M., Garrido, M., López-Vallejo, M.: ‘Real time FPGA implementation of an modulation classifier for electronic warfare applications’. Proc. European Signal Processing Conf., Barcelona, Spain, August 2011, pp. 1514–1518.
    6. 6)
      • 4. Naseem, I., Togneri, R., Bennamoun, M.: ‘Linear regression for face recognition’, IEEE Trans. Pattern Anal. Mach. Intell., 2010, 32, (11), pp. 2106–2112 (doi: 10.1109/TPAMI.2010.128).
    7. 7)
      • 3. Ma, D.Y., Chen, Y.M., Li, Q.M., Huang, C., Xu, S., Zou, Y.B.: ‘Registration with linear regression model in augmented reality’. Proc. Int. Conf. Science Automation and Engineering, Shanghai, China, June 2011, Vol. 2, pp. 520–523.
    8. 8)
      • 7. Garrido, M., Grajal, J.: ‘Procedimiento y arquitectura de circuito en pipeline para el cálculo de la regresión lineal’, ES Patent 2365883, 2011.
    9. 9)
      • 6. Fenton, O., Beardsmore, A., Lane, D.: ‘Software regression facility’, US Patent 20080127121 A1, 2008.
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