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A new last-level cache replacement policy for systems with a phase-change memory (PCM) main memory is presented. The proposed policy aims at reducing the write traffic to PCM by considering the fine-grained dirtiness of cache blocks when making a replacement decision. Experimental results show that the proposed policy reduces the write traffic to the PCM by 26 and 17% on average and up to 52 and 33% compared to not recently used and re-reference interval prediction, respectively.
References
-
-
1)
-
3. NRU: ‘Inside the Intel Itanium 2 Processor’. , 2002.
-
2)
-
2. Lee, S., Bahn, H., Noh, S.: ‘Characterizing memory write references for efficient management of hybrid PCM and DRAM memory’. Proc. IEEE MASCOTS, Singapore, July 2011, pp. 168–175.
-
3)
-
4. Jaleel, A., Theobald, K., Steely, S., Emer, J.: ‘High performance cache replacement using re-reference interval prediction (RRIP)’. Proc. ACM/IEEE ISCA, Saint-Malo, France, June 2010, pp. 60–71.
-
4)
-
1. Qureshi, M., Srinivasan, V., Rivers, J.: ‘Scalable high performance main memory system using phase-change memory technology’. Proc. ACM/IEEE ISCA, Austin, TX, USA, June 2009.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2013.1418
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