access icon free Impact of dynamic variability on the operation of CMOS inverter

The impact of dynamic variability due to low-frequency fluctuations on the operation of CMOS inverters, which constitute the basic component of SRAM cell, is investigated. The experimental methodology to characterise the effect of dynamic variability in a CMOS inverter is first established based on fast I–V measurements of the load current following the application of a ramp input voltage V in(t). It is shown that, for small ramp rise times, the load current characteristics I DD(V in) exhibit a huge sweep-to-sweep dispersion due to low-frequency noise. The impact of such dynamic variability sources on the inverter's output characteristics V out(V in) is finally demonstrated, revealing a 20% noise margin reduction for the smallest inverter cell.

Inspec keywords: SRAM chips; CMOS memory circuits; invertors

Other keywords: noise margin reduction; load current; SRAM cell; sweep-to-sweep dispersion; I-V measurements; dynamic variability impact; low-frequency noise; CMOS inverter

Subjects: Semiconductor storage; Memory circuits; CMOS integrated circuits; Power electronics, supply and supervisory circuits

References

    1. 1)
      • 7. Ioannidis, E.G., Haendler, S., Dimitriadis, C.A., Ghibaudo, G.: ‘Characterization and modeling of low frequency noise in CMOS inverters’, Solid-State Electron., 2013, 81, pp. 151156 (doi: 10.1016/j.sse.2012.12.001).
    2. 2)
      • 2. Asenov, A.: ‘Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 µm MOSFET's: a 3-D atomistic simulation study’, IEEE Trans. Electron Devices, 1998, 45, (12), pp. 25052513 (doi: 10.1109/16.735728).
    3. 3)
      • 1. Pelgrom, M.J.M., Duinmaijer, A.C.J., Welbers, A.P.G.: ‘Matching properties of MOS transistors’, IEEE J. Solid-State Circuits, 1989, 24, (5), pp. 1433 (doi: 10.1109/JSSC.1989.572629).
    4. 4)
      • 3. Hiramoto, T., Suzuki, M., Song, X., et al: ‘Direct measurement of correlation between SRAM noise margin and individual cell transistor variability by using device matrix array’, IEEE Trans. Electron Devices, 2011, 58, (8), pp. 22492256 (doi: 10.1109/TED.2011.2138142).
    5. 5)
      • 5. Takeuchi, K., Nagumo, T., Takeda, K., et al: ‘Direct observation of RTN-induced SRAM failure by accelerated testing and its application to product reliability assessment’. IEEE Proc. Symp. VLSI Technology, Honolulu, HI, June, 2010, pp. 189190.
    6. 6)
      • 4. Ghibaudo, G., Boutchacha, T.: ‘Electrical noise and RTS fluctuations in advanced CMOS devices’, Microelectron. Reliab., 2002, 42, (4–5), pp. 573582 (doi: 10.1016/S0026-2714(02)00025-2).
    7. 7)
      • 6. Josse, E., Parihar, S., Callen, O., et al: ‘A cost-effective low power platform for the 45-nm technology node’. Proc. IEEE Int. Electron Device Meeting, San Francisco, December, 2006, pp. 14.
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