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High-voltage EDMOS transistor with dual work function gate

High-voltage EDMOS transistor with dual work function gate

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A high-voltage extended drain MOS (EDMOS) transistor with a dual work function gate (DWFG) is discussed. This device enhances device performance by modifying the electric field in the channel. For DWFG EDMOS device fabrication, the polycrystalline silicon gates on the source and drain sides are doped by p + and n + ion implantation, respectively. Experimental results from the fabricated DWFG EDMOS devices show improved transconductance (g m), drain conductance (g ds) and specific on-resistance (R ON) characteristics without breakdown voltage reduction.

References

    1. 1)
      • 1. Bianchi, R.A., Monsieur, F., Blanchet, F., Raynaud, C., Noblanc, O.: ‘High voltage devices integration into advanced CMOS technologies’. IEDM'08, San Francisco, CA, USA, December 2008, pp. 137140.
    2. 2)
      • 2. Udrea, F.: ‘State-of the-art technologies and devices for high-voltage integrated circuits’, IET Circuits, Devices Syst., 2007, 1, (5), pp. 237240 (doi: 10.1049/iet-cds:20070025).
    3. 3)
      • 3. Ha, J.-B., Kang, H.-S., Baek, K.-J., Lee, J.-H.: ‘Enhancement of device performance in LDMOSFET by using dual-work-function-gate technique’, IEEE Electron Device Lett., 2010, 31, (8), pp. 848850 (doi: 10.1109/LED.2010.2051134).
    4. 4)
      • 4. Na, K.-Y., Baek, K.-J., Kim, Y.-S.: ‘N-channel dual-workfunction-gate MOSFET for analog circuit applications’, IEEE Trans. Electron Devices, 2012, 59, (12), pp. 32733279 (doi: 10.1109/TED.2012.2219865).
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