access icon free Power-efficient, PVT robust conductance cancellation method for gain enhancement

© The Institution of Engineering and Technology
Received 28/02/2013, Published

A power-efficient, process, voltage and temperature (PVT) robust gds cancellation method for gain enhancement is proposed. The method generates a negative conductance, which matches and cancels the positive conductance. This makes the gds cancellation method effective over process and wide temperature variation without the aid of external calibration or a tuning circuit. The method senses signals from cascode nodes instead of output nodes, making the method insensitive to output voltage swing. The simulation results of an example implementation in IBM 0.13 µm process show at least 22 dB DC gain enhancement over all process corners and temperatures ranging from − 20 to 80°C, with less than 9% power consumption overhead.

Inspec keywords: calibration; network analysis; circuit tuning

Other keywords: temperature -20 degC to 80 degC; external calibration; temperature variation; power-efficient process-voltage and temperature robust cancellation method; IBM process; size 0.13 mum; power-efficient PVT robust conductance cancellation method; positive conductance cancellation; cascode nodes; gain enhancement; tuning circuit; power consumption overhead; output voltage swing

Subjects: General circuit analysis and synthesis methods; Measurement standards and calibration

References

    1. 1)
      • 2. Amourah, M.M., Geiger, R.L.: ‘A high gain strategy with positive-feedback gain enhancement technique’. ISCAS, Sydney, Australia, 2001, pp. 631–634.
    2. 2)
      • 4. Jie, Y., Geiger, R.L.: ‘Fast-settling CMOS operational amplifiers with negative conductance voltage gain enhancement’. ISCAS, Sydney, Australia, 2001, pp. 228–231.
    3. 3)
      • 7. He, C., Jin, L., Chen, D., Geiger, R.: ‘Robust high-gain amplifier design using dynamical systems and bifurcation theory with digital postprocessing techniques’, IEEE Trans. Circuits Syst. I, 2007, 54, (5), pp. 964–973 (doi: 10.1109/TCSI.2007.895513).
    4. 4)
      • 3. Amourah, M.M., Geiger, R.L.: ‘All digital transistor high gain operational amplifier using positive feedback technique’. ISCAS, Scottsdale, AZ, USA, 2002, pp. I 701–704.
    5. 5)
      • 5. Jie, Y., Geiger, R.L.: ‘A high gain CMOS operational amplifier with negative conductance gain enhancement’. CICC, Orlando, FL, USA, 2002, pp. 337–340.
    6. 6)
      • 6. He, C., Chen, D., Geiger, R.L.: ‘A low-voltage compatible two-stage amplifier with ≥120 dB gain in standard digital CMOS’. ISCAS, Bangkok, Thailand, 2003, pp. 353–356.
    7. 7)
      • 1. Bult, K., Geelen, G.J.G.M.: ‘A fast-settling CMOS op amp for SC circuits with 90-dB DC gain’, IEEE J. Solid-State Circuits, 1990, 25, (6), pp. 1379–1384 (doi: 10.1109/4.62165).
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2013.0705
Loading

Related content

content/journals/10.1049/el.2013.0705
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading