© The Institution of Engineering and Technology
A new incremental ADC (IADC) is proposed which extends the order of a conventional incremental ADC from N to (2N − 1) by way of a two-step operation. For a given conversion time, the duration of each step can be optimised. For an Nth-order IADC, the performance is equivalent to that of a (2N − 1)-order converter. However, it only needs the same circuitry as the Nth-order one. The new IADC is hence more accurate, and also much more power-efficient than the conventional ones.
References
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1. Markus, J., Silva, J., Temes, G.C.: ‘Theory and applications of incremental ΔΣ converters’, IEEE Trans. Circuits Syst. I., 2004, 51, pp. 678–690 (doi: 10.1109/TCSI.2004.826202).
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2. Chen, C.-H., Crop, J., Chae, J., Chiang, P., Temes, G.C.: ‘A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits’. IEEE Int. Symp. on Circuits and Systems, Vancouver, BC, Canada, 2012.
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3. Mulliken, G., Adil, F., Cauwenberghs, G., Genov, R.: ‘Delta–sigma algorithmic analog-to-digital conversion’. IEEE Int. Symp. on Circuits and Systems, Scottsdale, AZ, USA, 2002.
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Mulliken, G., Adil, F., Cauwenberghs, G., Genov, R.: `Delta–sigma algorithmic analog-to-digital conversion', IEEE Int. Symp. on Circuits and Systems, 2002, Scottsdale, AZ, USA.
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J. Markus ,
J. Silva ,
G.C. Temes
.
Theory and applications of incremental ΔΣ converters.
IEEE Trans. Circuits Syst. I
,
4 ,
678 -
690
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6)
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Chen, C.-H., Crop, J., Chae, J., Chiang, P., Temes, G.C.: `A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits', IEEE Int. Symp. on Circuits and Systems, 2012, Vancouver, BC, Canada.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2013.0104
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content/journals/10.1049/el.2013.0104
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Two-step incremental analogue-to-digital converter