access icon free Model of hot-carrier degradation for lateral IGBT device on SOI substrate

A novel model for hot-carrier degradation in a lateral insulated gate bipolar transistor (IGBT) device on SOI substrate (SOI-LIGBT) is presented. The setup of the model is based on the existing hot-carrier degradation mechanism in a SOI-LIGBT and assisted by a lateral DMOS device on SOI substrate (SOI-LDMOS) with completely the same structure except for the doping type in the drain area. The model parameters have been extracted by the degradation measurement results and the validity of the proposed model in a SOI-LIGBT has been also verified.

Inspec keywords: hot carriers; MIS devices; insulated gate bipolar transistors; silicon-on-insulator; MOS integrated circuits; semiconductor doping

Other keywords: doping type; SOI substrate; hot-carrier degradation model; lateral IGBT device; LIGBT; degradation measurement; lateral insulated gate bipolar transistor; LDMOS; lateral DMOS device

Subjects: Semiconductor doping; Bipolar transistors; Insulated gate field effect transistors

References

    1. 1)
      • 1. Qiao, M., Jiang, L., Wang, M., et al: ‘High-voltage thick layer SOI technology for PDP scan driver IC’. Power Semiconductor Devices & IC's, (ISPSD), San Diego, CA, USA, 2011, pp. 180183.
    2. 2)
      • 3. Qian, Q., Sun, W., Liu, S., et al: ‘Novel hot-carrier degradation mechanisms in lateral insulated gate bipolar transistor on SOI substrate’, IEEE Trans. Electron Devices, 2011, 58, (4), pp. 11581163 (doi: 10.1109/TED.2011.2105494).
    3. 3)
      • 4. Liu, S., Sun, W., Qian, Q., et al: ‘Comparisons of hot-carrier degradation in SOI-LIGBT and SOI-LDMOS with different stress conditions’, Solid-State Electron., 2010, 52, (12), pp. 15981601 (doi: 10.1016/j.sse.2010.07.010).
    4. 4)
      • 5. Moens, P., Mertens, J., Bauwens, F., et al: ‘A comprehensive model for hot carrier degradation in LDMOS transistor’. Int. Reliability Physics Symp., Phoenix, AZ, USA, 2007, pp. 492497.
    5. 5)
      • 6. Riedlberger, E., Keller, R., Reisinger, H., et al: ‘Modeling the lifetime of a lateral DMOS transistor in repetitive clamping mode’. Int. Reliability Physics Symp., Anaheim, CA, USA, 2010, pp. 175181.
    6. 6)
      • 2. Gevinti, E., Cerati, L., Sambi, M., et al: ‘Novel 190V LIGBT-based ESD protection for 0.35 µm smart power technology realized on SOI substrate’. IEEE EOS/ESD Symp., Toscan, AZ, USA, 2008, pp. 211220.
    7. 7)
      • Qiao, M., Jiang, L., Wang, M.: `High-voltage thick layer SOI technology for PDP scan driver IC', Power Semiconductor Devices & IC's, (ISPSD), 2011, San Diego, CA, USA, p. 180–183.
    8. 8)
      • Gevinti, E., Cerati, L., Sambi, M.: `Novel 190V LIGBT-based ESD protection for 0.35 µm smart power technology realized on SOI substrate', IEEE EOS/ESD Symp., 2008, Toscan, AZ, USA, p. 211–220.
    9. 9)
    10. 10)
      • Riedlberger, E., Keller, R., Reisinger, H.: `Modeling the lifetime of a lateral DMOS transistor in repetitive clamping mode', Int. Reliability Physics Symp., 2010, Anaheim, CA, USA, p. 175–181.
    11. 11)
    12. 12)
      • Moens, P., Mertens, J., Bauwens, F.: `A comprehensive model for hot carrier degradation in LDMOS transistor', Int. Reliability Physics Symp., 2007, Phoenix, AZ, USA, p. 492–497.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2012.4036
Loading

Related content

content/journals/10.1049/el.2012.4036
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading