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High performance CSTBT with p-type buried layer

High performance CSTBT with p-type buried layer

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A novel high performance carrier stored trench bipolar transistor (CSTBT) with a p-type buried layer (PBL-CSTBT) is proposed. The p-type layer of the structure is formed by ion implantation at the bottom of the trench after a partial etching of the Pbase/Ncs layer and the fabrication process is fully compatible with the conventional CSTBT (C-CSTBT) structure. In comparison with the C-CSTBT without a buried layer, the novel structure offers not only high breakdown voltage, but also improved Eoff-Vce(on) trade-off characteristics.

References

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      • Li, Z., Qian, M., Zhang, B.: `TAC-IGBT: an improved IGBT structure', IEEE 21st Int. Symp. on Power Semiconductor Devices and IC's, (ISPSD), 2009, Barcelona, Spain, p. 124–127.
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      • Li, Z., Qian, M., Ma, R., Zhang, B., Li, Z.: `Trench IGBT with carrier bypass region', Int. Conf. Communications, Circuits and Systems, (ICCCAS), 2009, Milpitas, CA, USA, p. 624–627.
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      • Takahashi, T., Tomomatsu, Y., Sato, K.: `CSTBT', IEEE 20th Int. Symp. on Power Semiconductor Devices and IC's, (ISPSD), 2008, Orlando, FL, USA, p. 72–75.
    6. 6)
      • Nakamura, K., Sadamatsu, K., Oya, D., Shigeoka, H., Hatade, K.: `Wide cell pitch LPT(II)-CSTBT', IEEE 22nd Int. Symp. on Power Semiconductor Devices and IC's, (ISPSD), 2010, Hiroshima, Japan, p. 387–390.
    7. 7)
      • Haraguchi, Y., Honda, S., Nakata, K., Narazaki, A., Terasaki, Y.: `600V LPT-CSTBT', IEEE 23rd Int. Symp. on Power Semiconductor Devices and IC's, (ISPSD), 2011, San Diego, CA, USA, p. 68–71.
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