Simplified digital lock-in amplifier algorithm

Simplified digital lock-in amplifier algorithm

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The phase-sensitive or ‘lock-in’ amplifier is a fundamental tool in experimental physics, and is able to extract exceedingly small signals in the presence of noise. Recently, there has been some interest in portable or embedded lock-in amplifiers for instrumentation and sensing. One difficulty with digital lock-ins is the required degree of numerical precision. Presented is a fast algorithm for combined phase-sensitive multiplication and filtering. It exploits symmetry to reduce the number of arithmetic operations, and is suitable for low-power embedded devices. As well as being computationally much simpler than a direct digital implementation, the results presented show that it yields a lower error in the estimation of the underlying signal amplitude.


    1. 1)
    2. 2)
    3. 3)
    4. 4)
      • B.W. Bomar , V.K. Madisetti , D.B. Williams . (1998) Finite wordlength effects, The digital signal processing handbook.

Related content

This is a required field
Please enter a valid email address