http://iet.metastore.ingenta.com
1887

Effect of SiGe channel on pFET variability in 32 nm technology

Effect of SiGe channel on pFET variability in 32 nm technology

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The effect of a silicon germanium (SiGe) channel on pFET threshold voltage (VTH) mismatch in 32 nm high-K/metal-gate (HKMG) process is characterised. Additional variability is observed in the SiGe-channel pFET as compared with the traditional pFET with a silicon (Si) channel. Despite the extra VTH mismatch introduced by the SiGe channel, the traditional mismatch figure of merit from a Pelgrom plot (AVT) continuously scales down as technology advances from poly/SiON to HKMG process.

References

    1. 1)
    2. 2)
      • Takeuchi, K., Fukai, T., Tsunomura, T., Putra, A.T., Nishida, A., Kamohara, S., Hiramoto, T.: `Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies', IEDM Tech. Dig., 2007, Washington, DC, USA, p. 476–470.
    3. 3)
      • Luo, Z., Steegen, A., Eller, M.: `High performance and low power transistors integrated in 65 nm bulk CMOS technology', IEDM Tech. Dig., 2004, San Francisco, CA, USA, p. 661–664.
    4. 4)
      • Luo, Z., Rovedo, N., Ong, S.: `High performance transistor featured in an aggressively scaled 45 nm bulk CMOS technology', VLSI Symp. Tech. Dig., 2007, Kyoto, Japan, p. 16–17.
    5. 5)
      • Chen, X., Samavedam, S., Narayanan, V.: `A cost effective 32 nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process', VLSI Symp. Tech. Dig., 2008, Honolulu, HI, USA, p. 88–89.
    6. 6)
      • Krishnan, S., Kwon, U., Moumen, N.: `A manufacturable dual channel (Si and SiGe), high-K metal gate CMOS technology with multiple oxides for high performance and low power applications', IEDM Tech. Dig., 2011, Washington, DC.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2011.3830
Loading

Related content

content/journals/10.1049/el.2011.3830
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Correspondence
This article has following corresponding article(s):
Studied variations
This is a required field
Please enter a valid email address