SOI SJ high voltage device with linear variable doping interface thin silicon layer

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SOI SJ high voltage device with linear variable doping interface thin silicon layer

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A novel high concentration linear variable doping interface thin silicon layer (TSL) silicon-on-insulator (SOI) super junction (SJ) LDMOS is proposed. The design of the linear variable doping can deplete the high drift concentration. The proposed structure uses a TSL to achieve charge balance and eliminate substrate-assisted depletion effect. The dielectric electric field (EI) and the breakdown voltage (BV) of the TSL SOI SJ are 530 V/μm and 552 V with 30 µm length drift region and 1 µm-thick dielectric layer, respectively, and the specific on-resistance (Ron, sp) is 0.03403 Ω·cm2 and FOM (FOM=BV2/Ron,sp) is 8.95 MW/cm2, when gate voltage is 5 V.

Inspec keywords: semiconductor doping; MIS devices; silicon; dielectric materials; elemental semiconductors; silicon-on-insulator

Other keywords: Si; drift region; linear-variable doping interface TSL; drift concentration; voltage 5 V; thin-silicon layer; charge balance; SOI SJ high-voltage device; size 1 m; dielectric electric field; substrate-assisted depletion effect; breakdown voltage; size 30 m; silicon-on-insulator super-junction LDMOS; dielectric layer; voltage 552 V

Subjects: Semiconductor doping; Other semiconductor devices

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