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Parallel pipelined histogram architectures

Parallel pipelined histogram architectures

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Proposed is a unique cell histogram architecture which will process k data items in parallel to compute 2q histogram bins per time step. An array of m/2q cells computes an m-bin histogram with a speed-up factor of k; k≥2 makes it faster than current dual-ported memory implementations. Furthermore, simple mechanisms for conflict-free storing of the histogram bins into an external memory array are discussed.


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      • Shahbahrami, A., Hur, J.Y., Juulink, B., Wong, S.: `FPGA implementation of parallel histogram computation', 2ndHiPEAC Workshop on Reconfigurable Computing, 2008, Göteborg, Sweden, p. 63–72.
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