Frequency-to-digital conversion based on sampled phase-locked loop with third-order noise shaping

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Frequency-to-digital conversion based on sampled phase-locked loop with third-order noise shaping

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A new frequency-to-digital architecture based on a phase-locked loop (PLL) is presented, where the voltage controlled oscillator output is sampled before being fed back to one of the phase-frequency detector inputs. A frequency discriminator, located at the PLL sampled output, generates the converter output. Simple analytical models show that the sampling error is shaped by a third-order transfer function just like the quantisation error is shaped in a third-order sigma-delta modulator. The proposed architecture is suitable for integration in modern nanometre CMOS technologies, and it can be used as a FM demodulator.

Inspec keywords: phase locked loops; voltage-controlled oscillators; demodulators; transfer functions; CMOS integrated circuits; convertors; circuit noise

Other keywords: quantisation error; third-order transfer function; voltage controlled oscillator output; phase-frequency detector inputs; third-order noise shaping; third-order sigma-delta modulator; nanometre CMOS technologies; frequency discriminator; frequency-to-digital conversion; phase-locked loop

Subjects: Oscillators; CMOS integrated circuits; Modulators, demodulators, discriminators and mixers

References

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      • S. Cicero , Vaucher . (2002) Architectures for RF frequency synthesizers.
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      • Bax, W.T., Copeland, M.A., Riley, A.D.: `A single-loop second-order SD frequency discriminator', Proc. IEEE-CAS Region 8 Workshop Analog Mixed IC Design, 1996, p. 26–31.
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